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Verification Engineer

Intel


Location:
Bangalore
Date:
04/06/2018
2018-04-062018-05-05
Job Code:
JR0055305
Categories:
  • Engineering
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Job Details

Verification Engineer Careers at Intel in Bangalore, KA
   
Job ID: JR0055305
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Verification Engineer

Job Description
This position is with Integrated IP and Technology Group. This group performs development of IP building blocks and methodologies for Intel's System On Chip SoC solutions for the different market segments. In this position, the candidate will be responsible for verification of soft IP cores for Intel's next generation chips including SOCs for the different market segments.Verification Lead will be responsible for the execution and quality verification sign-off and interact with Performance , Power and SOC verification team.- Writing test cases and making scoreboard/infrastructure changes to the environment- Ownership/coding/enhancement of functional scoreboards/agents/sequences/monitors- Responsible for understanding architecture spec and deriving test cases / testplans- Need to be a key team player, while being highly energetic and motivated, independent and self-driven with minimal mentoring/hand-holding- Expected to help/drive in throughput test case setup/analysis/report of the DUT- Expected to define functional coverage/code/hit it through sequence enhancement and newer/directed test cases.


Qualifications

Master of Science or a Master of Technology degree in Electrical Engineering with more than 7 years of relevant industry experience or a Bachelor of Science Bachelor of Technology degree in Electrical Engineering with more than nine years of relevant industry experience. * Relevant ASIC design/validation experience in front end processes including RTL functional, performance and power verification.* Expertise in verification of design blocks IP for system-on-chip SoC components * Expertise in system verilog, and/ OVM or UVM based verification methodologies* Experience in OOP concepts, coverage based random validation * Experience in one/more of the following areas PCIe, USB, DP* Knowledge of scripting, SVA , UPF validation* Knowledge of IO interconnect , memory controllers, CPU architecture is a plus* Knowledge of considerations for performance, power and cost optimization is desirable Expected to be thorough with general verification concepts with System Verilog/OVM/UVM

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Legal Disclaimer:

Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews.   We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements.


   

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