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Validation Tech Lead

Intel


Location:
Santa Clara, CA
Date:
01/22/2018
2018-01-222018-02-20
Job Code:
JR0043874
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Job Details

Validation Tech Lead Careers at Intel in Santa Clara, CA
   
Job ID: JR0043874
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

Validation Tech Lead

Job Description
Define Validation Strategy and execution plans, working with stakeholders - he/she needs to understand architecture design, logic design, and system simulation. Define module interfaces/formats for simulation & validation. Candidate needs to perform all aspects of SoC validation, including defining and executing test plans and working with partner teams on emulation to ensure proper coverage towards high quality SoC TI. Will be excepted to work with IP/chassis teams to understand IP bug rates and weak areas to get higher coverage at SoC. Analyzes and reviews bug, coverage and execution data with senior management to propose actions to improve overall product quality. With the initial ramp in pre-silicon validation, he will be expected to get involved in post-silicon debug activities to drive overall success towards production.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position.Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Requirements:The candidate must have a MS in Computer Engineering or related fields w/ 8+ years of experience on the following fields:- Verification experience in FPGA, ASIC, CPU or custom IC designs.- Coherency and computer architecture experience- System Verilog and VMM/OVM/UVM. + Creating and documenting verification plansPreferred Requirements:6+ years of experience in the following fields:- Hardware Design, Verification and Validation Principles.- Verilog and System Verilog design of complex IP blocks working with high speed design- Knowledge of cache coherency or memory system verification- Design verification, Knowledge of UVM based methodologies.- Test bench architecture, test case development, functional coverage, coverage collection and analysis.- Microcontroller subsystem verification.- Formal verification methods property checking is desirable.- Strong verbal and written communication skills- Leadership skills and ability to interface/interact/influence cross-org stakeholders

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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