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Transceiver PHY IP Verification Engineer

Intel


Location:
San Jose, CA
Date:
08/21/2017
2017-08-212017-09-19
Job Code:
JR0029987
Categories:
  • Engineering
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Job Details

Transceiver PHY IP Verification Engineer Careers at Intel in San Jose, CA
   
Job ID: JR0029987
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations:
Job Type: College Grad

Transceiver PHY IP Verification Engineer

Job Description

As part of Intel, we will continue to apply Moore's Law to drive the future of field-programmable gate array FPGA technology.  The Programmable Solutions Group PSG has been delivering industry-leading custom logic solutions to customers since inventing the world's first reprogrammable logic device in 1984.  In order to take advantage of the many opportunities that we see in the future for FPGA's, PSG is looking for great verification engineers to join our team.

 

As a PHY IP verification engineer, you will be part of a wonderful team of professionals. You will define and develop system validation environments and test suites.

 

You will be responsible for the development of methodologies, execution of validation plans, and debug of failures. You will develop an understanding of multiple system areas as you interact with the architecture, design, pre-silicon validation, and post-silicon validation teams to ensure the quality of our IP cores and silicon.

 

If you have a love for hardware and software, a desire to be part of a great team, and a desire to work on cutting edge transceiver products, the Intel PSG Transceiver PHY IP team may be a good fit for you.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Requirements:
- Must have a Bachelor's or Master's degree in Electrical Engineering or related field.
- At the bachelor's level you must have unrestricted right to work in the US without requiring sponsorship.

Minimum of 1 year of experience with:
-Verilog, SystemVerilog, UVM methodology design verification and debug

Preferred Qualifications
Experience with:
-Developing and implementing test plans
-Developing and debugging test benches and designs using ModelSim, VCS, and/or NCSim.
-Scripting language including Perl and/or TCL
-Hardware bringup / debug / validation

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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