Technical Leader: ASIC Physical Design

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Hardware
  • Job Type
  • Technology Interest
    Cloud and Data Center, Internet of Everything, Networking
  • Job Id

Title: Technical Lead, ASIC Physical Design

Location: San Jose, CA



Our creative and talented team as Physical Design Lead in San Jose, CA. You will work with ASIC Front-end teams to understand chip architecture and drive physical aspects early in the design cycle, driving them to refine their design for physical design closure. As a member of this team you will be involved in creating cutting edge next generation networking chips. You will be the lead to drive the backend process through the entire Implementation flow including floor planning, Placement, CDC checks, static timing verification and equivalence checks, with special focus on power and die size optimization.




  • Responsible for floor planning of full chip and key sub chips, handing off your floorplans and physical synthesis results to physical implementation.
  • Responsible for driving timing closure through physical synthesis and P&R tools and working with ASIC vendors.
  • As member of physical/implementation design team, drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress.
  • Resolve design and flow issues related to physical design, identify potential solutions and drive execution.




 You are a HW engineer with 10+ years of related work experience with a broad mix of technologies including:

  • All aspects of ASIC integration including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
  • Hierarchical design approach, top-down design, budgeting, timing and physical convergence.
  • Experience on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain
  • Experience with large designs (>100M gates) utilizing state of the art sub 16/14 nm technologies.
  • Familiarity with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and power/ thermal management, power islands.


You should also have hands on experience with the following Tool sets

  • Floor planning and P&R tools:   Cadence Innovus & Synopsys ICC2),
  • Synthesis Tools: Synopsys DC/DCG
  • Formal Verification : Synopsys Formality and Cadence LEC
  • Static Timing verification (Primetime/PTPX).
  • Familiarity with Physical Design Verification Flows is a plus.
  • Scripting: TCL, Perl is required; Python is a plus


Bachelor's or a Master’s Degree in Electrical or Computer Engineering required


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