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Sr. Structure Design Engineer

Intel


Location:
Bangalore
Date:
04/06/2018
2018-04-062018-05-05
Job Code:
JR0056053
Categories:
  • Engineering
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Job Details

Sr. Structure Design Engineer Careers at Intel in Bangalore, KA
   
Job ID: JR0056053
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Sr. Structure Design Engineer

Job Description
Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.


Qualifications

Qualifications: BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering with minimum of 10 years in VLSI Design with expertise in RTL-to-GDSII flow, floor planning, Clock tree synthesis and block-level/chip-level signoff Needs to be familiar with all aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning and hard IP integration. Experience solving SoC issues such as ESD strategies, mixed signal block integration, and package interactions. Familiar with hierarchical design approach, top-down design, area budgeting and physical verification convergence. Must have experience on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain. A detailed understanding of database management issues will be required. Expertise using leading-edge EDA tools Synopsys, Cadence or Mentor Graphics From a CAD tool perspective, experience with floorplanning tools, P&R flows and physical design verification flows is required.Make, Perl and Python expertise is nice to have. Motivation to drive an exciting project. Very effective team player. Excellent verbal and written communication skillsPreferred Qualifications:Experience in custom / data-path implementation is highly desirable. Should be be able to specify and drive IP requirements in the physical domain Ability to plan, execute, course correct and optimize blocks and SoC level implementations. Ability to provide mentorship and guidance to junior engineers.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


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