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Soft IP Design Micro Architect

Intel


Location:
Kulim
Date:
04/06/2018
2018-04-062018-05-05
Job Code:
JR0056021
Categories:
  • Engineering
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Job Details

Soft IP Design Micro Architect Careers at Intel in Kulim, KDH
   
Job ID: JR0056021
Job Category: Engineering
Primary Location: Kulim, KDH MY
Other Locations:
Job Type: Experienced Hire

Soft IP Design Micro Architect

Job Description

Looking for passionate, motivated and self-driven candidate who likes to deal with different challenges and make a difference. Position requires experience in digital logic design and exposure to pre/post-silicon validation.

Candidate will be responsible for logic design micro architecture in SPI/eSPI Team under PEG-ITG-CIG-PID group, responsibilities include and not limited to:

- defines micro architecture specification of the design

- implements design in RTL and qualifies with various strategies/tools/methods

- checks the design for Lint, synthesizability, DFX, Analyze Clock crossing, Power, Performance implications during the design.

The candidate must work closely with the Architect and Validation teams in determining the proper implementation/validation strategy for new design, defining and feedback on specifications, develop White Box Coverage plans, review design codes for efficiency/coverage and drive any paradigm shifts needed in design implementation.

The candidate will be actively engaged in risk analysis and validation recommendation for product Tapeouts etc.The candidate is also responsible for mentoring junior members of the team and improving the overall technical bench strength of the organization.

Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical leadership skills, passion for design/tools and methodology and strong influencing skills.

Must have strong orientation for Quality, 'Commit & Deliver' mindset, drive Innovation/ efficiencies and have strong strategic thinking to come up with paradigm shift solutions to critical design/validation challenges.


Qualifications

You must possess a minimum of Bachelor Degree in Computer Engineering or Electrical Engineering Master Degree in Computer Engineering or Electrical Engineering preferred.

Minimum Requirements:

- 10+ years of experience in relevant logic design position and must have gone through multiple project cycles to gather in-depth experience.

- 10+ years of experience in digital logic design with various tools and methodologies including: System Verilog, Perl, VCS/Synopsys simulators, Lint, synthesis, Clock Domain Crossing tools, DFX Scan and Power.

- 10+ years of experience in PC Architecture.

- Capable in developing MAS micro architecture specification, white-box testplan and coverage, assertions, power intent with UPF, synthesis constraints, scan coverage, etc.

- Capable in developing functional verification testplan, tests contents and coverage points for verification purpose based on High Level Architecture spec.

- Experienced in VLSI or Structural and Physical design flow/methodology.

- Experience in SPI, USB, PCI express or any Industrial standard bus protocol would be added value.

- Strong analyzing and debugging skill, and creative in problem solving.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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