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SOC Silicon Design Graduate Trainee

Intel


Location:
Penang
Date:
08/21/2017
2017-08-212017-09-19
Job Code:
JR0005035
Categories:
  • Engineering
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Job Details

SOC Silicon Design Graduate Trainee Careers at Intel in Penang, PNG
   
Job ID: JR0005035
Job Category: Intern/Student
Primary Location: Penang, PNG MY
Other Locations:
Job Type:

SOC Silicon Design Graduate Trainee

Job Description

You must possess a Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering. Additional qualifications include: - Familiarity with Very Large Scale Integration VLSI Complementary Metal-Oxide Semiconductor CMOS logic circuit design - Well versed in UNIX*, C programming and relevant Computer Aided Design CAD tools



Qualifications
Job Description: In this position, you will be involving in the training, design and development of next generation SOC/CPU for wide range of Intel products ranging from Client PC , smartphone, tablet to wearable. Your responsibilities will include some of the following but not limited to: - Assist design unit owner in Register Transfer Level RTL model functional validation. Use CAD tool extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions. Verify the circuit behavior against the original simulation model and first silicon. - Define VLSI Structural Design methodology and developing design flows. Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration. Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power. - Develop Analog IP on next generation deep submicron process for the Intel's SOC, perform tasks related to Very-large-scale integration VLSI complementary metal-oxide-semiconductor CMOS IC design, Solid state physics and physical layout. Such tasks may include: Circuit design of high speed clocking related circuits [phase-locked loop PLL, delay-locked loop DLL, bandgap] or high voltage input/output IO [double data rate DDR/LPDDR, General-purpose input/output GPIO, OPIO]. - Responsible for Integration of Third party IPs -- Synthesis, functional and/or timing convergence, and pre and post-si debug of IPs developed by various external vendors as well as within the company. Handling of signals crossing power planes and clock domains, industry standard protocols including hardware and software details dealing with Memory LPDDR, storage eMMC, SATA, UFS, peripherals PCIe, USB, and MIPI interfaces in SOC devices. System integration dealing with Si/ Platform/ FW/ MW/ drivers/ OS/ Apps on Android Windows-based tablets and phones.

   

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