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SoC Physical Design Engineer

Intel


Location:
Bangalore
Date:
04/06/2018
2018-04-062018-05-05
Job Code:
JR0055641
Categories:
  • Engineering
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Job Details

SoC Physical Design Engineer Careers at Intel in Bangalore, KA
   
Job ID: JR0055641
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

SoC Physical Design Engineer

Job Description
SoC Physical Design Engineers are responsible for the design and development of electronic components. We are seeking an individual who is a technical leader in the RTL to GDS phase of the ASIC design flow and has previously played a key technical/lead role in development and delivery of leading edge physical databases for ASICs, SOCs or IPs.A successful candidate would be knowledgeable in most aspects of physical design from RTL to GDS, understand the interactions between each step of the physical design flow, and be proficient in the Layout/APR stages of the flow and the interactions for effective timing closure and related trade-offs on power/performance and area efficient design best practices.The Layout/APR stages of the flow include block/full-chip floor-planning, top-level connectivity management, power-grid design, block level floor-planning, block level LVS/DRC closure and roll-up of multiple blocks to ensure overall LVS/DRC cleanliness. The candidate must be self-motivated to seek constant improvements in the physical design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. The candidate must be able to lead the project execution with effective communication and develop/train/mentor the team.


Qualifications

You should possess a relevant educational qualification, BE/BTech or ME/MTech in Electrical Engineering/Computer Engineering or equivalent with 6 to 10 years design experience in the structural / physical design domain. Additional qualifications include:- Extensive knowledge & hands-on experience in structural/physical design methodology, flows and relevant EDA tools.- Experience in leading the final delivery of a block/IP/SOC thru Tape-in - Hands-on expertise with scripting languages such as Perl, TCL to enhance design automation and flow improvements.- Experience of mentoring team members in their technical development.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Legal Disclaimer:

Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews.   We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements.


   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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