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SoC Physical Design Engineer

Intel


Location:
Bangalore
Date:
04/06/2018
2018-04-062018-05-05
Job Code:
JR0055650
Categories:
  • Engineering
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Job Details

SoC Physical Design Engineer Careers at Intel in Bangalore, KA
   
Job ID: JR0055650
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

SoC Physical Design Engineer

Job Description
Seeking an individual who is a technical leader in the RTL to GDS phase of the SOC/ASIC design flow and has previously played a key technical/lead role in development and delivery of leading edge physical databases for ASICs, SOCsCandidate exposure to trade-offs on power/performance and area efficient design best practices.The candidate must be able to lead the project execution with effective communication and develop/train/mentor the teamPerforms all aspects of the SoC/ASIC design flow from synthesis, place and route, timing and power to create a design database that is ready for manufacturing. The candidate must also possess strong initiative, good communication and analytical/problem solving skills, team player and be able to work within a diverse team environment


Qualifications

Bachelors/Masters Or equivalent in Electrical/Electronics stream And/Or in VLSI systems.Experience 9 years till 13 yearsA successful candidate would be knowledgeable in most aspects of physical design from RTL to GDS, understand the relation between each step of the physical design flow and be proficient in the different stages of floorplanning and Placement and routing of the design. Candidate should have worked on timing closure challenges and possess good working knowledge of interactions between timing analysis tool and PnR tool.The Layout/PnR stages of the flow includes full-chip floor-planning, block/top connectivity management, power grid design, LVS/DRC and timing closureCandidate should have experience of static and dynamic power/IR flow and fixes. Knowledge of place and route DRC, analysis and fixes. Awareness of DFM techniques and low power implementation are desirable. Aware of Chip finishing for Tape-In/Out process is a plusCandidate should be well versed with shell/tool scripting for e.g. Perl, TCL etcThe candidate must be self-motivated to seek constant improvements in the physical design methodologies.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Legal Disclaimer:

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It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews.   We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements.


   

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