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SoC Physical Design Engineer


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Job Details

SoC Physical Design Engineer Careers at Intel in Bangalore, KA
Job ID: JR0055648
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

SoC Physical Design Engineer

Job Description
Performs all aspects of the SoC/ASIC/IP design flow from synthesis, place and route, timing and power to create a design database that is ready for manufacturing. The candidate must also possess strong initiative, good communication and analytical/problem solving skills, team player and be able to work within a diverse team environment.


Bachelors/Masters in Electrical/Electronics stream And/Or in VLSI systemsExperience : 6 Years till 10 YearsA successful candidate would be knowledgeable in most aspects of physical design from RTL to GDS, understand the relation between each step of the physical design flow and be proficient in the different stages of floorplanning and Placement and routing of the design. Candidate should have worked on timing closure challenges and possess good working knowledge of interactions between timing analysis tool and PnR tool.The Layout/PnR stages of the flow includes block/full-chip floor-planning, block/top connectivity management, power grid design, block level LVS/DRC and timing closure.Candidate should have experience of static and dynamic power/IR flow and fixes. Knowledge of place and route DRC, analysis and fixes.Awareness of DFM techniques and low power implementation are desirable.Candidate should be well versed with shell/tool scripting for e.g. Perl, TCL etcThe candidate must be self-motivated to seek constant improvements in the physical design methodologies.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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