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SoC DFT Lead

Intel


Location:
Bangalore
Date:
01/19/2018
2018-01-192018-02-17
Job Code:
JR0037355
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Job Details

SoC DFT Lead Careers at Intel in Bangalore, KA
   
Job ID: JR0037355
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

SoC DFT Lead

Job Description

Oversees definition, design, verification, and documentation for SoC System on a Chip development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.


Qualifications

SoC DFT expert 9-15yrsIn this position, you will be responsible for design and validation of various DFT features such as Scan, MBIST, JTAG, BScan, analog DFT, etc. for Intel's leading edge SoC designs. You will work with post-silicon teams to comprehend their usage models, test time/fault coverage/data collection goals, and tester capabilities and limitations. You will work with IP and integration design teams to understand the design and functional-mode behaviors of the logic and circuits. You will micro-architect DFT features which are compatible with the specific product/post-silicon requirements and constraints. You will assist in the RTL and schematic implementation and pre-silicon validation and debug of these DFT features. You will also be expected to deliver high-quality documentation for consumption by the post-silicon teams who will use the DFT features. Strong knowledge of DFT architectures & methodologies. This includes Scan, ATPG, Mbist, BScan, IO DFx, analog DFT, JTAG, Boundary scan, etc. Proven knowledge of Verilog & System Verilog, RTL design and micro-architecture skills. Strong knowledge of SoC tools/methodology OVM, Saola, ACE, VCS*, Lintra, CDC, Synthesis, Spyglass, Tessent ATPG/MBIST tools, Synopsys ATPG tools, design compiler, etc. Strong debug skills and demonstrated experiences in Perl & TCL scripting. Strong Si debug skills, ATE requirements and understanding of volume test requirements.Strong Communications skills and the ability to effectively work with cross functional teams.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews.   We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements.


   

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