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Senior SoC Physical Design Engineer


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Senior SoC Physical Design Engineer Careers at Intel in Bangalore, KA
Job ID: JR0047905
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Senior SoC Physical Design Engineer

Job Description
The Scalable Performance CPU Development Group SDG is searching for an energetic and passionate senior physical design engineer who is ready to be part of new growth areas in server product family. We are looking for someone who has passion around improving the way we solve complex problems through team work as well as their own direct contributions. Direct Responsibilities: Implements physical design, physical verification, and documentation for SoC System on a Chip development. Determines chip floorplan, working with packaging and design teams. Defines interfaces/formats, timing closure points, timing/physical constraints at module and chip level. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of SoC physical design flow from high-level design to synthesis, place and route, DFx, timing and power to create a design database that is ready for manufacturing. The ideal candidate should be able to demonstrate the following behaviors: Ability to work effectively with both internal and external teams/customers. Experience in working on silicon physical designs which include processor cores and custom logic. Strong problem solving, written and verbal communication skills. Capable of working in a high performing team to deliver the results required from the organization. Facilitator of direct and open communication, diversity of opinion, and debate.


BS degree in Electrical Engineering or other related field of study with a minimum of 7+ years of relevant experience in SOC/IP physical design and verification or MS degree with 5+ years of directly related SOC physical Design Industry Experience. Candidates must have the following: Proven expertise in Silicon product development and relevant SoC/IP/ASIC physical design and verification. Understand system and package implications of the silicon design decisions. Expertise in physical design and integration of design blocks, IPs to system-on-chip . Experience with design implementation of various type of external interfaces, like DDR, PCIe or similar. The ability to work as an individual and as part of a team to deliver a product starting from floor plan, block implementation, full chip physical design, verification and timing closure. Preferred Skills : Experience with implementation of ASIC based and SoC designs. Experience in building physical design environments and flows based on industry standard tools and methodologies. Experience with implementing and working with multiple fab's and technology nodes

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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