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Senior SoC DFT Engineer


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Job Details

Senior SoC DFT Engineer Careers at Intel in Bangalore, KA
Job ID: JR0054361
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Senior SoC DFT Engineer

Job Description
The Scalable Performance CPU Development Group SDG is searching for an energetic, passionate and process oriented DFx Engineer who has extensive experience in implementation and verification of DFx features for multiple SoCs. We are looking for someone who has passion around improving the way we solve complex problems through team work as well as their own direct contributions. Direct Responsibilities: In this role you will be responsible for working with stakeholders to architect DFT/DFD requirements, implementation and verification of the same in pre silicon as well as supporting silicon validation for leading edge SoC designs. Includes responsibility for supporting manufacturing and testability of our products, design & verification using Scan ATPG tools for pattern generation and coverage, debug and gate level simulation. Also includes experience in MBIST, LBIST, JTAG, BScan design implementation and verification. Responsibilities include delivery of high-quality documentation for consumption by the post-silicon teams using the DFx features. The ideal candidate will be able to demonstrate the following behaviors: Ability to work effectively with both internal and external teams/customers. Ability to mentor other engineers and technically guide them. Strong problem solving/leadership skills. Strong written and verbal communication skills. Facilitator of direct and open communication, diversity of opinion, and debate.


BS degree in Electrical Engineering, Computer Engineering or other related field of study with a minimum of 7+ years or MS degree with 5+ years of directly related industry experience in SOC/IP DFx Design and Verification. Candidates must have the following: Proven expertise in Silicon product development. Experience in development of RTL design and validation of IP and SoC DFx. Experience in working closely with physical design team to ensure timing closure for DFx IP/SoC logic at full chip, RTL design of DFx IP and SoC logic, development of test env, test plan and test execution. The ability work as an individual and as part of a team to deliver a product starting from the creation of the spec, design and verification. Need a good understanding of System Verilog, scripting languages like shell scripting, PERL and verification methodologies like UVM, sound understanding of test strategies, debug flows, ATPG tools and GLS. Working experience with post-silicon teams to comprehend usage models, test time and tester capabilities. Strong Si debug skills, ATE requirements and understanding of volume test requirements. Strong Communications skills and the ability to effectively work with cross functional teams.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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