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Senior Logic Designer

Intel


Location:
Folsom, CA
Date:
01/19/2018
2018-01-192018-02-17
Job Code:
JR0048496
Categories:
  • Engineering
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Job Details

Senior Logic Designer Careers at Intel in Folsom, CA
   
Job ID: JR0048496
Job Category: Engineering
Primary Location: Folsom, CA US
Other Locations: California, Santa Clara; ,
Job Type: Experienced Hire

Senior Logic Designer

Job Description

The Mixed Signal IP Solutions Group MIG within the Platform Engineering Group is looking for a Logic Design Engineer.

You will work on high-speed digital design and is targeted towards low power optimized implementations of high speed IPs.

Your responsibilities will include but are not limited to implementing RTL in System Verilog, validating the design, synthesizing the design and closing timing.

You will also have an opportunity to work on high-level understanding of the architecture through to the details of timing, and will contribute to specifications at multiple levels, including the HAS and MAS microarchitecture spec.

You must be able to balance design trade-offs with modularity, scalability, DFX requirements, power, area, and performance.

The ideal candidate should exhibit behavioral traits that indicate excellent written and verbal communication skills, as they are critical on a small, fast-moving team.

As part of a growing, dynamic new business, the candidate must also be successful working with a small team and manage multiple tasks and changing requirements in an innovative environment.


Qualifications

Minimum Requirements:

  • The successful candidate will possess a BS, MS, or PhD degree in Electrical Engineering with a minimum of 7+ years of relevant industry experience
  • Low power design, understanding analog design concerns and driving to an optimal solution between analog and digital designs, familiarity with pre-silicon and post-silicon validation.

Preferred Requirements:

Experience in the following areas/ skills are desired:

  • Logic design using System Verilog
  • Micro-architecture trade-offs and
  • Low-power design using UPF and clock gating
  • Multiple clock domain design
  • State machine design
  • Simulation and debug experience using VCS/Verdi7
  • Synthesis and speed path debug
  • Perl / C-shell

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.



Other Locations

California, Santa Clara; ,


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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