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Senior IP-SoC Structural Design Engineer


Hillsboro, OR
Job Code:
  • Engineering
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Job Details

Senior IPCareers at Intel inSoC Structural Design Engineer
Job ID: JR0053287
Job Category: Engineering
Primary Location: Hillsboro, OR US
Other Locations: US, California, Santa Clara
Job Type: Experienced Hire

Senior IP-SoC Structural Design Engineer

Job Description
Job Description

As a Sr IP-SoC Structural Design Engineer, you will be working alongside Elite IP and SoC design teams within the Scalable Performance CPU Development Group delivering next-generation Xeon products and related IPs for Server markets.

We are looking for a high-energy and passionate hands on physical design team member to work with a diverse team and partner with experienced physical design engineers as part of the Structural Design Expert Team in the IP organization.

You will be fluent in all aspects of IP physical design flow from high-level block design to synthesis, place and route and timing and power convergence to build a design database that is ready for manufacturing.

Your responsibilities will include all aspects of RTL2GDSII physical design flow convergence including but not be limited to:

  • Block-level floor planning, interconnect planning and UPF based power delivery methodology
  • Logic synthesis of design blocks using Synopsys Design Compiler DCT- Formal Equivalence Verification FEV using Cadence's Conformal tool
  • Auto Place-and-Route APR using Synopsys ICC tools
  • Timing and power verification using Synopsys PrimeTime as well as Intel tools
  • Layout Verification and DRC analysis.


Minimum Requirements:

You will have a BS/MS degree in Computer Engineering, Electrical Engineering or Computer Science

Experience/Skills: 10+ with BS or 8+ with MS years of industry experience in SOC/IP physical design including but not limited to a good understanding of the following:-

  • Constraint understanding, generation, clock stamping and timing closure
  • Synthesis with Synopsys Design Compiler DCT- DFT, Scan Insertion, and coverage analysis- Multiple Power Domain Analysis using standard Power Formats UPF/CPF- Floorplanning, Interconnect and Circuit Design and analysis
  • Place and Route and clock tree synthesis with Synopsys ICC- Static Timing Analysis with Synopsys Primetime and power analysis with PTPX- Formal equivalence, Layout Verification and DRC analysis
  • Proficient in scripting PERL and/or TCL

You should exhibit behavioral traits that indicate:

  • Self-motivator with strong analytical skills
  • Ability to work independently and at different levels of abstraction
  • Excellent interpersonal skills, including written and verbal communication
  • Ability to work as a team and collaborate in a high-paced atmosphere

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Other Locations

US, California, Santa Clara

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.


As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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