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Senior Digital IC Design

Intel


Location:
Bangalore
Date:
01/22/2018
2018-01-222018-02-20
Job Code:
JR0033854
Categories:
  • Engineering
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Job Details

Senior Digital IC Design Careers at Intel in Bangalore, KA
   
Job ID: JR0033854
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Senior Digital IC Design

Job Description

Job Description: In this role, the Senior Digital IC Design Engineer will be part of team contributing to Silicon Photonics Solution Group's mission to transform and lead datacenter connectivity and enable Intel's differentiation in the networking space. As senior Engineer, the individual will be involved in developing key digital & mixed signal designs from architecture to product. Responsibilities will include driving system specifications, defining digital circuit architectures and enabling designs meeting power, performance and cost for next generation optical interconnects. As part of the team developing key components the engineer must be able to work collaboratively leading block level development. equipment and other hardware systems. Determines creative design approaches and parameters. Analyzes equipment to establish operating data. Conducts experimental tests and evaluates results. Applies and uses independent evaluation to selects components and equipment based on analysis of specifications and reliability. Evaluates practical capability of vendor to support product development.Minimum QualificationsThe ideal candidate should have MS in Electrical Engineering or Computer Engineering. 10+ years of experience in SERDES / High Speed Digital Development.Able to design through various phases of the ASIC/SOC digital design process - Product definition, Architecture, RTL design using Verilog, system Verilog, verification, syntheses, P&R and STA, Test bench development, Functional verification, Timing analysis, Power consumption and power integrity analysis, Guiding the physical design and DFT efforts for your designs Must be hands-on and possess solid design and architecture experience for chip and system definition, low power design techniques, multiple power domain design, clock gating, multi VT design, DFx, CPF and CDC tools. Support product validation, ATE test and QUAL teams during high volume ramp-up.Deep knowledge of CMOS/BiCMOS Process . Experience with integrated analog mixed signal designs. Good understanding of low noise PLL, Clocking and data recovery architectures. Good understanding of Signal Integrity and Channel modeling. Experienced with Digital and Mixed signal design flow using Synopsys, Cadence and Mentor tools. Excellent oral and written communication skills.


Qualifications

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.


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It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews.   We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements.


   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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