Senior Design Verification Engineer

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Hardware
  • Job Type
    Professional
  • Technology Interest
    Internet of Everything
  • Job Id
    1208016
New
Participate in the architecture and verification of complex, high-performance, and highly integrated ASICs used in Cisco's networking products.

Responsibilities:

* Participate in architecture definition and modeling.
* Contribute in micro-architecture specification and reviews.
* Partake in verification environment architecture and methodology.
* Carry out testplanning and execution of testplan.
* Cooperate with design team members to effectively test, verify, and debug DUT for successful tapeout.
* Engage in post-silicon bringup and debug in the lab.
* Mentor and enable other engineers.
* Lead and oversee design verification efforts of a cluster of blocks.

Skills Required:

* Experience in high-performance ASIC verification.
* Good understanding of ASIC design and verification methodologies and flows.
* Hands-on experience with HVL and HDL languages and tools, scripting and programming languages (verilog, SV, C++, Perl, etc.).
* Proficient in object oriented programming.
* Good understanding of random stimulus generation methodology.
* UVM knowledge a plus.
* Good problem solving skills.
* Good communication skills and a team player.
* Networking knowledge preferred, but not essential.

Qualification:

* Complex ASIC verification experience.
* Proficient in object oriented programming.
* Good understanding of random stimulus generation methodology.
* Good communication and teamwork skills.

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