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Reliability Verification Engineer

Intel


Location:
San Jose, CA
Date:
08/18/2017
2017-08-182017-09-16
Job Code:
JR0031780
Categories:
  • Engineering
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Job Details

Reliability Verification Engineer Careers at Intel in San Jose, CA
   
Job ID: JR0031780
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations:
Job Type:

Reliability Verification Engineer

Job Description

As part of Intel, we will continue to apply Moore’s Law to drive the future of field-programmable gate array (FPGA) technology.  The Programmable Solutions Group (PSG) has been delivering industry-leading custom logic solutions to customers since inventing the world's first reprogrammable logic device in 1984.  In order to deliver high performance and high quality FPGA to customers, PSG is looking for great Reliability Verification Engineers to join our team.

As a key member of FPGA full chip integration team, you will be responsible for all aspects of reliability verification for our next generation full chip development. Responsibilities include power distribution network design and validation, IR spec definition and verification, physical and reliability collateral generation and database management, cross functional collaboration to verify, debug, and sign-off system level reliability including power IR/EM, signal reliability, and product DPM.

Please be informed that Intel is proactively trying to find candidates for a position and that may, or may not, be available for all location(s) at this time. If you're interested in this position, we encourage you to apply, and our hiring team will be glad to contact you if/when relevant.



Qualifications
• BS/MS in Electrical Engineering, Computer Science, or related, • 5 years of semiconductor experience (any silicon design) • Experience with 2 cycles of digital power distribution network design, chip and system level signal and power reliability verification including power IR/EM and signal RV using Totem and RedHawk • 3 years of experience in Verilog, Spice, full custom and ASIC design flows. ADDITIONAL (PREFERRED) QUALIFICATIONS • Experience in flow definition on large and complex designs. Able to take flow definition to implementation and execution • Experience of PERL/Python, TCL, Linux Shells


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
   

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