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  • Intel
  • Penang PNG MY
  • 09/18/2017
  • Engineering
Responsible for developing full chip & IP test methods, on-chip DFT Design-for-Test definition and verification, test vector generation and coverage analysis, and 1st silicon debug for Intel's FPGA products.Responsible for deploying PPV Test Program collateral and readiness for testability and m...  More Details
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  • Intel
  • Folsom, CA United States
  • 09/18/2017
  • Engineering
Your responsibilities will include but not be limited to:- Debug Security failures arising from validation testing and customer issues.- Drive product through Security Design life- Define Security Validation testing methodologies to ensure- Performing failure analysis using available tools- Designin...  More Details
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  • Intel
  • Penang PNG MY
  • 09/18/2017
  • Engineering
• Develop binning and yield strategy to meet requirements of the newest FPGA products. This includes defining bin-splits, developing models to improve yield/binning predictability, establishing targets/limits to control yield, and the development/bring-up of binning circuits.• Drive for yield optimi...  More Details
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  • Intel
  • Penang PNG MY
  • 09/18/2017
  • Engineering
Responsible for developing full chip & IP test methods, on-chip DFT (Design-for-Test) definition and verification, test vector generation and coverage analysis, and 1st silicon debug for Intel’s FPGA products.Responsible for deploying Sort Class Test Program collateral and readiness for testabil...  More Details
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  • Intel
  • Penang PNG MY
  • 09/18/2017
  • Engineering
Responsible for ensuring the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp.Make significant contributions to design, development and validation of testability circuits.Evaluation, development and debug of complex test methods.De...  More Details
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