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Pre-Silicon Reliability Engineer

Intel


Location:
Folsom, CA
Date:
02/19/2018
2018-02-192018-03-20
Job Code:
JR0051446
Categories:
  • Engineering
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Job Details

PreCareers at Intel inSilicon Reliability Engineer
   
Job ID: JR0051446
Job Category: Engineering
Primary Location: Folsom, CA US
Other Locations:
Job Type: Experienced Hire

Pre-Silicon Reliability Engineer

Job Description

As a member of the NAND Memory Design team focusing on Quality and Reliability you will be responsible for working with Device, Design, DA, and Layout personnel in the defining, developing, and delivering of one or more of the following key company and customer reliability objectives:

  • Aging (transistor aging)
  • EM & IR (electro migration and IR voltage drop)
  • PERC (physical electrical rule check)
  • EOS/SOA (electrical overstress)

You will also be responsible for one or more of the following:

  • The direct execution of, or the assisting/training of others, in the pre-silicon reliability validation checks, to ensure NAND product compliance to spec
  • Making recommendations to Device, Design, DA, and Layout regarding the changes and/or the mitigation required to achieve a quality output/product
  • The development of new and the maintenance of existing pre-silicon reliability validation flows, and the documentation of same
  • Validation of the pre-silicon reliability checks, which requires a good understanding of the phenomena under test, as well as, the measurement and comparison to post-silicon results
  • The continuous improvement of NAND product quality and reliability
  • Managing the schedule and delivery/development of new Reliability checks and the execution of same


Qualifications

The candidate should have as a minimum a BS in Physics or EE. The ideal Pre-Silicon Reliability Engineering candidate would have 5+ years or an MS and 3+ years of industry experience with a subset of/in the following areas and associated tools: Circuit related A good basic understanding of MOS transistor operation and circuit design A basic understanding of MOS transistor layout design and parasitics Front-End CAD tools Transistor simulators; (experience with 1 or more of the following circuit simulators is a must) Synopsys: Customsim (XA, CCK, EOS, & RA), HSPICE, Finesim Cadence: XPS, Spectre ProPlus: NanoSpice Giga Mentor: Analog FastSPICE (AFS) Transistor Aging tools; (experience with transistor aging and one of the following Aging models is a plus) Synopsys: MOSRA Cadence: RelExpert EM/IR drop/R: CustomSim_RA, Apache_Totem & Redhawk, … (experience with one or more EM & IR flows is a must) Back-End CAD tools PERC: Mentor PERC, Cadence PVS, Insight ERC, … Parasitic extraction: StarRC, xRC, Totem, … Software and Programming tools Languages/tools: Python, C++, TCL, Ruby, mySQL, excel/office, wiki, … Design Environments Cadence ADE L, XL, & GXL Schematic & Layout tools: Cadence Virtuoso, Synopsys CustomDesigner General knowledge/skill A comprehensive knowledge of current industry Reliability tools, methods, and practices The knowledge and experience required to, from scratch put into place complete Reliability sign-off methodologies Knowledge regarding the effect/interaction of the die package, stacked die, and the PCB on die Reliability Skill in the design and execution of, test structures and experiments, required to validate changes made to improve overall die Reliability A working knowledge of Reliability failure mechanisms, for a variety of circuit configurations/architectures, and mitigation techniques for same Knowledge of the required/preferred Layout and DRC rules for ensuring quality die Reliability

Inside this Business Group

Non-Volatile Solutions Memory Group:  The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices.  The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
   

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