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Pre-Si Verification Engineer

Intel


Location:
San Jose, CA
Date:
09/25/2017
2017-09-252017-10-24
Job Code:
JR0035031
Categories:
  • Engineering
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Job Details

PreCareers at Intel inSi Verification Engineer
   
Job ID: JR0035031
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations:
Job Type: College Grad

Pre-Si Verification Engineer

Job Description

As a Design Verification Engineer for high speed digital design you will work at Sub-system and Full Chip level to validate the design in an energetic design engineering team and management environment to develop next generation FPGA platforms for the data center and networking markets. You will closely work with IP Development teams to verify FPGA SOCs with high speed serial protocols such as Ethernet, UPI and PCIe using state of the art technologies. You will be part of a team that strives for innovation and consistent methodologies to solve challenging problem, while pushing for a very high quality product to tapeout. You will create verification architecture and test-plan specifications. You will be responsible for design verification of a complex design while creating a culture of industry standard best practices and methodologies. You will be working with partners across multiple-sites and both during pre-si and post-si phase of the project.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.

Minimum Requirements:

The candidate must have a Master Degree in Electrical Engineering or related field.

2+ years of experience on the following fields:

  • Verification experience in FPGA, ASIC or custom IC designs.
  • High-speed transceiver protocols including PCI Express or UPI.
  • System Verilog, VMM/UVM.
  • Creating and documenting verification plans.

Preferred Requirements:

1+ years of experience in the following fields:

  • Hardware Design, Verification and Validation Principles.
  • Verilog and System Verilog design of complex IP blocks working with high speed design.
  • Design verification, Knowledge of UVM based methodologies.
  • Test bench architecture, test case development, functional coverage, coverage collection and analysis.
  • Microcontroller subsystem verification.
  • Formal verification methods property checking is desirable Strong verbal and written communication skills.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
   

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