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Pre-Post Silicon Validation Engineer, Senior-Staff

Intel


Location:
Kulim
Date:
01/19/2018
2018-01-192018-02-17
Job Code:
JR0048170
Categories:
  • Engineering
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Job Details

PreCareers at Intel inPost Silicon Validation Engineer, Senior
   
Job ID: JR0048170
Job Category: Engineering
Primary Location: Kulim, KDH MY
Other Locations: Malaysia, Penang;
Job Type: Experienced Hire

Pre-Post Silicon Validation Engineer, Senior-Staff

Job Description

As a Pre/Post Silicon Validation Engineer, you are required to creates, defines and develops system validation environment & test suites. Uses & applies emulation & platform-level tools & techniques to ensure performance to spec.

You are responsible for the development of methodologies, execution of validation plans, and debug of failures. Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features.

You are responsible in validating the functionality of new architectural features of next generation designs by developing test plans, tests content, coverage points or test tools.You are focal point between a number of Architecture, Design and Validation teams within Intel and across different sites.


Qualifications

  • Bachelor's/Master's in Hardware Engineering or Electrical/Electronics Engineering or Computer Engineering or Computer Science with minimum 5 years for Senior position or 8 years for Staff position of related work experience.
  • Candidate with experience in CPU/SoC/Chipset/Platform System Validation is preferable.
  • Strong knowledge and skills of Intel IA or ARM IA Architecture will be a plus.

Solid understanding and experience in any of the following architecture:

  • Power Management architecture who familiar in PMC feature, VID setting, Gate/Chip level power management transition state & etc.
  • Memory architecture who familiar in Cache/Memory structure, Memory to CPU ALU/CC transition state, Memory Mapping & etc.
  • USB architecture who familiar in USB Bulk/Interrupt/Isochronous transfer, Type of USB, Host/Device relationship, Transmission & etc.
  • PCIe architecture who familiar in PCIe interconnect, link, Lane, Configuration, Interrupt, I/O Read/Write, PCIe Layer, Form Factor & etc.oWiFi/GPS/Bluetooth/RF architecture who familiar in Wireless LLC characteristic, Data transition, I/O Read Write, Authentication, RF transmission & etc.
  • Storage architecture who familiar in eMMC/SD Card/UFS/HDD Data transfer, I/O Read Write, DMA, & etc.
  • Good working knowledge in C++/Python SW programming and scripting knowledge of Verilog/VHDL and EDA design tools is a plus.
  • Excellent written and oral communications and experience working in a cross functional team environment are essential.
  • Possess strong problem solving, analytical and debug skills.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.



Other Locations

Malaysia, Penang;

   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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