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Package Design Engineer

Intel


Location:
Singapore
Date:
08/18/2017
2017-08-182017-09-16
Job Code:
JR0008535
Categories:
  • Engineering
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Job Details

Package Design Engineer Careers at Intel in Singapore, Central Singapore
   
Job ID: JR0008535
Job Category: Engineering
Primary Location: Singapore, Central Singapore SG
Other Locations:
Job Type:

Package Design Engineer

Job Description

The Connected Home Division (CHD) is seeking an experienced Package Design Engineer. The successful candidate will be based in our R&D office in Singapore and will work closely with engineering teams in Singapore as well as other CHD R&D teams across the globe.

Job Description:

Define packaging solutions for highly innovative integrated circuits, meeting adequate mechanical, thermal and electrical performance with the goal to achieve lowest package and system level cost.

Co-design with chip designer, system engineering and PCB design teams during the development stage to optimize pad layout and pin map for most cost effective package and system.

Independently plan, design and develop quality custom lead frame/substrate/module with supporting electrical simulation to reduce cross-talk, IR drop, and noise issues of the device.

Technical lead for implementing packaging solutions at OSAT assembly site and/or internal assembly site. Ensure optimized package design which meets the assembly design rules of the selected assembly site. Work with the assembly partner to mitigate any potential risk and improve situation to meet yield target within the project milestone requirement.

Co-work with NPI manager to prepare assembly site readiness for continuous uninterrupted flow from wafer fab-out to quality packaged sample meeting the required NPI schedule.

Maintain complete set of product specific packaging related drawings, and reports.



Qualifications
- Bachelor / Master degree in Electrical Engineering / Mechanical Engineering / Material Science with more than 5 years experience in the field of IC Packaging Design and Layout. - Package design experience using Cadence SIP/APD/Sigrity UPD or Mentor Xpedition and AutoCAD is a must. - Understand performance and cost trade-offs for different layout and assembly rules. - Extensive manufacturing process knowledge regarding wafer bumping, substrate and lead frame manufacturing and assembly of wire bond and flip chip packages is required. - Experience using Ansys SIWave, HFSS and ICEPak will be an advantage. - Possesses good analytical, communication and organization skills.

   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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