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Mixed Signal Design Environment Optimization Specialist

Intel


Location:
Santa Clara, CA
Date:
01/15/2018
2018-01-152018-02-13
Job Code:
JR0048467
Categories:
  • Engineering
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Job Details

Mixed Signal Design Environment Optimization Specialist Careers at Intel in Santa Clara, CA
   
Job ID: JR0048467
Job Category: Engineering Management
Primary Location: Santa Clara, CA US
Other Locations: Arizona, Phoenix; California, Folsom;
Job Type: Experienced Hire

Mixed Signal Design Environment Optimization Specialist

Job Description

In this position you will need to  get results across boundaries, ensure an inclusive work environment, and coordinate with internal and external to MIG organizations to optimize the spending and utilization of MIGs overall compute infrastructure.

The goal is to optimize the use of our compute and license assets. You will need to develop plans for assets usage and track actual performance to those plans. Some of the key skills and tasks will include identifying and analyzing problems, planning and scheduling daily tasks and using judgement on a variety of problems requiring deviation from standard practices. Inadequacies and erroneous decisions would cause moderate inconvenience and expense.

This role will dig into compute infrastructure to look at how we are using it, what we are doing with it and come back with recommendations on how we can better optimize the assets.
 


Qualifications

Minimum Qualifications:

  • Bachelor of Science degree or Master of Science degree in Electrical Engineering, or a related educational qualification. 
  • 5+ years of experience in Silicon Design and Validation
  • Prior successful silicon development leadership experience either in a comparable complex technical program management role or in a silicon development engineering manager/technical lead role
  • Excellent communication, negotiating and stakeholder management skills.
  • Self-driven with strong sense of ownership.

 
Preferred Qualifications:

  • Familiarity with complete design development cycle from Technology Readiness through Qualification for Volume Manufacturing 
  • Experience with design development tools/flows and integration challenges.
  • Proven ability to work cross-sites, across time zones and with different cultures
  • Proven ability to drive decision-making across multiple levels of management up to senior level (GM,VP).

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.



Other Locations

Arizona, Phoenix; California, Folsom;


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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