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MIG Global Program Manager

Intel


Location:
Santa Clara, CA
Date:
04/06/2018
2018-04-062018-05-05
Job Code:
JR0047767
Categories:
  • Engineering
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Job Details

MIG Global Program Manager Careers at Intel in Santa Clara, CA
   
Job ID: JR0047767
Job Category: General
Primary Location: Santa Clara, CA US
Other Locations: US, Arizona, Phoenix;US, California, Folsom
Job Type: Experienced Hire

MIG Global Program Manager

Job Description
Within the Integrated IP and Technologies Group ITG, the Mixed-signal IP solutions Group MIG is chartered with delivering timely, competitive and reusable mixed-signal IP for Plug-n-Play in an IP subsystem or SOC and its platform. MIG supports product development teams in smartphones, tablets, client PCs and data center product lines as well as IOT, New Devices and the Intel Custom Foundry. The MIG portfolio of solutions includes high-speed IOs and on-package IOs e.g. PCIe3, SATA3, TBT, MIPI, pOPIO , memory PHY e.g. LPDDR4, WIO2, USB PHY USB2.0, 3.0, 3.1, Ethernet PHY e.g. 10G-KR, 100G-KR4, Display PHY e.g. DP/eDP, DSI, HDMI, Voltage Regulators e.g. LDO, SCVR/LCVR and a variety of analog building blocks such as PLLs RNG entropy source. MIG is a large global organization with several vertical IP development teams supported by horizontal enabling functions such as Technology & Methodology Office, Design Automation, Layout, Electrical Validation, Signal Integrity & Power Delivery. The candidate will be part of the MIG Program Management Office PMO and responsible for MIG deliverables, from planning to PRQ to several SOC development teams supporting DCG, CCG, iCDG, IOTG, PSG, ICF and others. This role will be responsible for directing a team of program managers. Responsibilities will include but not be limited to the following: Work closely with ITG Planning team, BU planning team and MIG vertical teams to anticipate future IP needs and capture them for IP roadmap planning. Work with SOC teams to define, capture and aggregate actual IP requests and with MIG teams and our partners e.g. EIG to prepare the proposed response from ITG represent MIG in the product POP process. Constantly drive for reuse and look for opportunities to optimize across the aggregated project list voltage rails, PVT corners, etc. Work with MIG vertical teams to turn IP requests into actual MIG configurations for development planning. Work with Subsystem/SOC teams and with MIG vertical teams to close the Landing Zone for each IP configuration and to establish a POR LZ + schedule in support of Test Chip or SOC development schedule. Understand product requirements, architecture, floor-plan, potential derivatives in order to translate them into specific IP requirements power management, area, DFx, chassis compliance, bump map, etc. Be the primary MIG interface and elevation path for the SOC team during execution through SOC tape-in, post-Si debug, any necessary stepping, all the way to PRQ and launch. Create an atmosphere of trust and foster the excellent collaboration with both subsystem/ SOC teams and MIG internal teams that will be conducive to anticipation or timely resolution of issues. Drive MIG teams towards excellent performance against schedule and high quality deliverables that meet or exceed expectations from the subsystem/SOC integration teams. Manage change effectively understand and balance the business and MIG and ITG needs. Be the voice of our partners in internal forums. Work collaboratively with other MIG PMs and similar functions in partner organizations to continually improve MIG ITG/PEG processes and infrastructure and with MIG Technology & Methodology Office to ensure that learning is shared and that we work with SOC teams and with partners and suppliers e.g. TD, DTS, std cells library team, etc to identify opportunities to increase our cadence while maintaining quality and competitiveness of our solutions.


Qualifications

Minimum Qualifications: Bachelor of Science degree or Master of Science degree in Electrical Engineering, or a related educational qualification. 15+ years of experience in Silicon Design and Validation. Prior successful silicon development leadership experience either in a comparable complex technical program management role, in a silicon development engineering manager/technical lead role or possibly in a related engineering field such as SOC DA or Design Technology providing that the role and responsibilities gave close exposure to SOC development challenges. Excellent communication, negotiating and stakeholder management skills. Self-driven with strong sense of ownership. Desired Qualifications: Familiarity with complete SOC development cycle from Technology Readiness through Qualification for Volume Manufacturing with experience on several projects does not have to be all at Intel and experience external to Intel could actually be a plus. Experience with SOC development tools/flows and integration challenges. Note that this is more important than in depth expertise in MIG specialties such as Analog/Circuit design. Experience working with Post-Silicon teams. Proven ability to work cross-sites, across time zones and with different cultures. Proven ability to drive decision-making across multiple levels of management up to senior level GM,VP.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.



Other Locations

US, Arizona, Phoenix;US, California, Folsom


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

Position of Trust. This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Talent Consultant.

   

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