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IP Verification Engineer


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Job Details

IP Verification Engineer Careers at Intel in Penang, PNG
Job ID: JR0017597
Job Category: Engineering
Primary Location: Penang, PNG MY
Other Locations:
Job Type:

IP Verification Engineer

Job Description

The Programmable IP Engineering group is responsible for High Speed Protocol IP development, which includes participating in high-level product specifications, logic/RTL design and implementation, RTL verification, IP FPGA emulation prototyping, validation and debugging.

As an IP Design Engineer focusing on IP Verification & Validation, you will be responsible for carrying out design validation for Intel next generation IP’s across the Intel FPGA IP product portfolios. The charter of IP verification & validation team is to verify and validate the IP for robust functionality from functional simulation, FPGA emulation prototyping, to complex system level environment. The verification and validation areas encompass IP’s for external memory interface protocols (eg. DRAM, SRAM) and high-speed transceiver protocols (eg. PCIe, Ethernet, Interlaken, JESD204B, UPI, Serial Lite, Rapid IO, HDMI, DP, SDI ). Your specific responsibilities may include but are not limited to the following:

  • Create comprehensive verification and validation plan based on IP/FPGA architecture specifications and carry out all the IP validation tasks. The plan encompasses functional, system level and hardware verification and validation perspectives.
  • Developing IP/subsystem/system level testbench, create tests, and necessary coverage goals based on specification to verify the implementation. Writing directed and random test cases, debugging failures, filing and closing bugs.
  • Review verification and validation results against the coverage goals. Writing, analyzing and achieving coverage metrics.
  • Work with cross-functional teams and prepare/support IP functional validation tests for IP bring-up on actual FPGA development kits.
  • Build IP FPGA emulation prototypes, creating and establishing IP subsystem/solution validation coverage strategy and standardized framework, drive system test design implementation and overall IP system validation on HW, maximize FPGA hardware capability to bring substantial improvement to IP quality & usability for Intel FPGA IP product portfolios.
  • Developing verification and validation tools and flows, as needed.
  • Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time-to-market

• BSEE/MSEE/PhD, with experience in FPGA, custom IC or ASIC design and/or verification • Experience in FPGA, custom IC or ASIC design, demonstrated excellence in any of the product development areas from architecture, design, validation to product. • Experience using advanced system design and validation methodologies and technologies (such as FPGA prototyping, emulation, simulation and co-emulation) • Experience using advanced verification methodologies (such as UVM, OVM, VMM, System Verilog, constrained-random stimulus generation, assertion-based verification, and functional coverage techniques) is a strong plus • Experience creating and executing validation plans • Familiarity or experience in RTL design with Verilog and/or VHDL is a strong plus • Familiarity or experience in embedded SW & HW design is a strong plus • Knowledge of any memory interface protocol (such as DRAM, SRAM) or high speed serial system interfaces (such as PCIe, Ethernet, IEEE 1588, UPI, JESD204B, CPRI or Serial Rapid IO, HDMI, DP, SDI) is a strong plus • Familiarity with Perl, TCL and shell scripts is a plus.


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