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IP Structural Design Engineer

Intel


Location:
Hillsboro, OR
Date:
01/22/2018
2018-01-222018-02-20
Job Code:
JR0040464
Categories:
  • Engineering
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Job Details

IP Structural Design Engineer Careers at Intel in Hillsboro, OR
   
Job ID: JR0040464
Job Category: Engineering
Primary Location: Hillsboro, OR US
Other Locations:
Job Type: Experienced Hire

IP Structural Design Engineer

Job Description

Your responsibilities will include but not be limited to:

- Block-level floor planning - Logic synthesis of design blocks

- Formal Equivalence Verification FEV - Auto Place-and-Route APR using Synopsys ICC tools - Timing verification using Synopsys PrimeTime as well as Intel tools - Physical verification - Layout vs. Schematic LVS, Design Rule Checks DRC, Electrical Rule Checks ERC, and Design for Manufacturability checks DFM - Analog signal specific requirements/checks- Assist in the preparation of the full-chip layout design database for introduction to manufacturing


Qualifications

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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