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Intel Custom Foundry Tape-out Execution: Full Chip Integration

Intel


Location:
Shanghai
Date:
08/18/2017
2017-08-182017-09-16
Job Code:
JR0019166
Categories:
  • Engineering
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Job Details

Intel Custom Foundry TapeCareers at Intel inout Execution: Full Chip Integration
   
Job ID: JR0019166
Job Category: General
Primary Location: Shanghai, Shanghai CN
Other Locations:
Job Type:

Intel Custom Foundry Tape-out Execution: Full Chip Integration

Job Description

Job Description: The Foundry Product Tape Out Execution is the primary technical interface between the customer and internal engineering teams, with focus on ensuring high quality Customer Tape-out, which meets/beats industry standard throughput.

General Focus Areas in this Role:

The position is required to work on customer’s site to participate the tapeout related tasks including physical implementation, timing signoff, reliability verification and DRC/LVS verification.

* Lead customer Tape-out Execution for advanced lithography nodes
* Participate in development and update of Tape-out quality Checklists and Paranoia
* Interface with customer lead technical engineer(s) and functional area leaders
* Understand customer's technical requests and needs and translate into an Intel Custom Foundry response
* Identify customer's skill and methodology gaps and provide support to enable them to tape-out on Intel process technology
* Ensure industry standard Tape-out throughput is met, and drive reduction opportunities
 



Qualifications
General Qualifications * 10+ years of proven success on ASIC tapeout and management experience * Ability to support COT/ASIC customers from early design stage through tapeout and provide professional recommendation in design stage * Work with customer as a team to accomplish the tapeout tasks with hand-on EDA tool skill set * Ability to work well across Intel Custom Foundry and with customer's engineering team * Strong brainstorming and problem solving skills * Good organization skills and ability to develop a plan of action to address technical challenges * Successful applied experience in the areas listed below in the Specific Focus Areas: * Familiar with ASIC design methodology, including hierarchical design methodology, low power design methodology and IP integration check * Familiar with APR flow including floorplan, I/O assignment, power plan full chip CTS topology and ECO methodology * Familiar with STA timing verification flow, reliability analysis flow such as IR/EM drop analysis. * Familiar with Layout verification rule including DRC/LVS/DFM , ESD/Latch-up rule and tapeout cleanup review * Fluent in Chinese, Japanese or Korea is a plus.


Position of Trust. This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Talent Consultant.
   

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