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HW SoC Design Engineer-CDG JER

Intel


Location:
Jeralem, IL
Date:
08/18/2017
2017-08-182017-09-16
Job Code:
JR0014385
Categories:
  • Engineering
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Job Details

HW SoC Design EngineerCareers at Intel inCDG JER
   
Job ID: JR0014385
Job Category: Engineering
Primary Location: Jerusalem, IL
Other Locations:
Job Type: Experienced Hire

HW SoC Design Engineer-CDG JER

Job Description
Conducts or participates in multidisciplinary research in the design, development, testing and utilization of information processing hardware and/or electrical components, mechanisms, materials, and/or circuitry, processes, packaging, and cabinetry for central processing units CPUs and/or peripheral equipment. Prepares specifications, evaluates vendors, and analyzes test reports. Ensures products conform to standards and specifications. Develops plans and cost estimates and assesses projects to analyze risk. Develops procedures, analysis and design for computer components, products, and systems. Initiates, guides, and coordinates overall design and development of new ideas and products. Responds to customer/client requests or events as they occur. Develops solutions to problems utilizing formal education and judgement.


Qualifications

Job DescriptionJoin Client Department Group which responsible for state of the art Intel SoC. As a member of the IP Design team, you will have responsibilities across all phases of IP design. Including micro-architecture specification, design, and debug of complex logic for high performance, and low power design targets. You will own all aspects of development of large SOC blocks, including Internal and external IP integration. This role will interface with other internal and external design groups. Participate in design/architecture reviews, work with validation team towards pre-silicon verification and flow automation, emulation and engage in post-silicon bring up activities. Scripting and programming experience using Perl, TCL, and Make.QualificationsMinimum Qualifications:- BSc in Electrical or Computer Engineering is required, at least 3+ years' experience with the following:- RTL Logic Design experience, vast knowledge on SystemVerilog/VHDL- Experience with High speed, Low Power Designs and Implementation Technique, knowledge of UPF and Power Intent Verification.- Proficiency in Front End Tools and Methodologies.- Experience in authoring Micro-Architecture/Design Specifications and Converting them to Design. - Perform Front End Integration tasks including: Lint, CDC, Synthesis, and ECO. - Experience with Multiple Clock Domains and Asynchronous Interfaces.- Experience in DFT Methodologies and Formal Verification Tools.- Familiarity with Scripting Languages like Gmake/Perl/Tcl/Python.

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