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HW/RTL Design Engineer

Intel


Location:
Santa Clara, CA
Date:
08/21/2017
2017-08-212017-09-19
Job Code:
JR0024948
Categories:
  • Engineering
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Job Details

HW/RTL Design Engineer Careers at Intel in Santa Clara, CA
   
Job ID: JR0024948
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type:

HW/RTL Design Engineer

Job Description

Join the 5G mobile revolution at Intel as part of the NGS organization within the Platform Engineering Group. We are looking for an experienced engineer to drive the digital design of the L1 PHY and MAC layers for advanced modem prototypes. You will report to the Director of System and HW engineering and work with a team of digital design engineers that develops advanced high bandwidth, low latency Tx/Rx transceiver chains in the baseband modem. You will be responsible for the definition, design, implementation and verification of complex digital modem blocks and sub-systems as part of modem ASIC/FPGA development. 
We are looking for candidates who can analyze complex algorithms and have the ability to provide feedback to the systems team, propose architecture alternatives and derive fixed-point implementations. Project deliverables include micro-architecture designs, RTL code, simulation models and reference codes, test benches and associated documentation. The role includes supporting firmware and RF teams with verification and bring-up of FPGA and ASIC modem prototypes, working closely with standards and algorithm teams to develop cutting edge wireless solutions and achieve program goals. The role includes mentoring junior engineers in a team environment. 
 
We are seeking candidates at different levels. Main job function is as follows.
•    Frontend digital design leading up to synthesis; system-level architecture and interface definition; microarchitecture and RTL development; developing HW blocks for wireless modem and debugging; some DFT and backend work
•    Functional verification and timing sign-off to physical design engineers

Minimum qualifications
The position requires a BS, MS or PhD in Electrical or Computer Engineering or similar discipline and at least 7 years of industry experience, including the following. 
•    Expert-level coding experience in Verilog/VHDL/System Verilog
•    Experience in ASIC frontend design for cellular (HSPA/LTE) Modem Baseband or Wi-Fi PHY receiver and transmitter blocks in a leading chipset company; experience having designed HW blocks (e.g., MIMO detector, FEC encoder/decoder, FFT/IFFT, Baseband filter, Interleaver, Equalizer, Channel Estimator, etc.) and followed through multiple product development cycles from microarchitecture to silicon; in-depth understanding of SoC architectures, peripherals, buses/interconnects and power management 
•    Expert in ASIC frontend design and synthesis tools (including Synopsys DC) and Lint/Formal Verification/CDC checking tools 
•    Experience in developing test benches for functional verification, RTL debugging and timing sign-off; and in formal verification methodologies including UVM/OVM and System Verilog assertions

Additional qualifications
•    Experience in scripting and automation tools (perl/tcl/gmake/python)
•    Experience with VCS, Verdi, and Spyglass
•    Experience in DFT methodologies, formal verification tools and physical design is a plus
•    Understanding of bus architectures (AXI or similar), Baseband/RFIC interfaces, Network-on-Chip and various CPU/DSP architectures desirable
•    Experience in post-silicon debugging, working in lab environment with reference boards and FPGA prototypes desirable
•    Familiar with ECO flows and tools
 



Qualifications


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