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Graphics Post Si Validation Engineer

Intel


Location:
Folsom, CA
Date:
04/06/2018
2018-04-062018-05-05
Job Code:
JR0054320
Categories:
  • Engineering
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Job Details

Graphics Post Si Validation Engineer Careers at Intel in Folsom, CA
   
Job ID: JR0054320
Job Category: Engineering
Primary Location: Folsom, CA US
Other Locations:
Job Type: Experienced Hire

Graphics Post Si Validation Engineer

Job Description

This responsible for Graphics Hardware Validation and Debug related activities covering the various Features of Processor Graphics like 3D, GTI, blitter, and GPGPU, Media, Display for post-silicon validation and debug. From a technical debug perspective, this role drives a regular debug forum for the team to help expedite debugs and make sure the appropriate external stakeholders are engaged. And when appropriate, form task force sessions to drive more urgent issues to resolution. The Post Si-Calidation Engineer will be expected to leverage best known methods and tools from existing Intel validation organizations.

Responsibilities will include but not be limited to:

  • Develop post-si validation test strategies, plans, and schedules,
  • Drive Execution of the written test plans and procedures
  • Plan scheduling of weekly tasks for meeting medium and long-term validation deliverables
  • Monitor progress against schedule communicating status
  • Identify and collect pertinent data to influence decisions when presenting to various management forums
  • Drive issue resolution with software and hardware development teams
  • Enhancing existing pre/post-si validation methodology and processes


Qualifications

Minimum Skills/Experience (Must Have to be Considered)

  • BS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 2+ years of post-graduate work experience in Post Silicon Debug /Validation and/or Emulation with a BS Decree OR 1+ years of post-graduate work experience with a Master’s Degree

Preferred Skills/Experience (Nice to Have but candidates lacking the below experience will still be considered)

  • 3+ years of semiconductor industry/high technology based experience Graphics knowledge / HW validation background
  • Knowledge of Windows/MacOS driver environment.
  • Device Driver and Kernel level debugging knowledge
  • RTL debug knowledge
  • Demonstrated excellent problem solving skills

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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