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Graphics HW Engineer

Intel


Location:
Bangalore
Date:
09/25/2017
2017-09-252017-10-24
Job Code:
JR0035645
Categories:
  • Engineering
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Job Details

Graphics HW Engineer Careers at Intel in Bangalore, KA
   
Job ID: JR0035645
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Graphics HW Engineer

Job Description

The candidate will be part of the Graphics Hardware system Validation teams in Visual and Parallel Computing Group (VPG) Bangalore, working on platform bring up, and graphics  systems validation, power and performance debugs. VPG is responsible for delivering integrated graphics IP for Intel's various products.

Qualifications:

Master or Bachelor of Engineering degree in Electronics or Computer Engineering with 2+ years' experience in graphics platform setup, post silicon functional validation/performance and power measurements

Should have basic understanding of Computer architecture, micro controller/microprocessor and/or graphics architecture/design , Experience with industry standard automation and scripting (C/C++/Shell programming/PERL/Python) to conduct efficient and reliable GPU performance and power measurements, Basic experience with the lab hardware equipment like DAQ, Logic Analyzer/O-scope and associated interfaces required to validate graphics, Media and Display.

Good analytical ability, problem solving and communication skills

Skill set

  • Solid understanding of Computer System Architecture. Knowledge of Microprocessor, Chipset, and 3D Graphics
  • Domain : good understanding of 3D, Media OR Display graphics pipeline (DirectX,OpenGL/OpenCL API’s/standards/specifications, Media Codecs, Display Standards) would be added advantage
  • Experience with ITP, Logic Analyzers*, Oscilloscopes, Scan dumps, and in-circuit Emulators
  • Excellent post-silicon/emulation debug skills (problem solving skills). Should have worked at least 3-5 yrs in post-si validation of any ASICs/SoC projects.
  • Failure reproduction in lower level validation (in emulation and pre-si simulations) to improve debug throughput
  • Working knowledge of standard post-Si debug and regression tools/methodologies. Also any emulation tools. DFX methodologies and tools usage.
  • Experience in Graphics Hardware-Software interfacing and debug would be plus
  • Knowledge of Software programming. Good programming skills in C/C++ and scripting (such as Perl or Ruby)
  • Good written and verbal communication skills and ability to be effective as a member of a multi-site development team
  • Strong interpersonal communications and self-driven skills
  • Familiarity with any bug tracking tools
  • Should be ready to travel for on-site support on the debug/test plan development (need basis)
  • Passion for validation and debug.

    Responsibilities

  • Responsible for Post-Si validation of Intel internal Graphics Cores (3D , Media, Power Mgmt and Display). Includes validation in Emulation/FPGA
  • Own, scope and drive the development of post-silicon verification test plans for few units in 3D-graphics pipeline.
  • Ability to Define test scenarios, write test cases, validate system level new features, regressions execution, track/analyze failures and debug.
  • Collaboratively work with the partner teams from design Software , platform to quickly root cause the test failures
  • Support SW driver/WHQL/benchmarks / media workloads/ Display Compliance test suites failure debug
  • Support test plans across base and derivate projects and different stepping within the project.
  • Independently work with architects/designers/pre-si validation/tech leads/SW driver team/SW-simulation/Emulation teams in driving the test plan reviews, and bug fixes to closure.
  • Interface with cross-site functional teams in different time zones to drive the validation.
  • Set up work groups/task forces to drive any focused validation tasks/debugs.
  • Review bugs, post-mortem of bug escapes and propose methods to catch bugs early
  • Analyze impact on performance/power and drive the fixes/workarounds as per project milestone priorities
  • Understand usage models (driver) and bring in scenarios early in emulation to validate to minimize escapes
  • Mentor and guide junior engineers in writing test cases, executing test plans. Provide direction on debug both in emulation and post-Si
  • Track the progress of quality/coverage goals. Provide periodic updates to program management on progress and escalate issues on time
  • Driver improvements/efficiencies in validation. Write technical papers for internal/external technical conferences in 3D graphics domain


Qualifications

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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