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FPGA Logic Design Engineer


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Job Details

FPGA Logic Design Engineer Careers at Intel in Shanghai, Shanghai
Job ID: JR0009959
Job Category: Engineering
Primary Location: Shanghai, Shanghai CN
Other Locations:
Job Type:

FPGA Logic Design Engineer

Job Description

Intel DCG DEG CPD is looking for an FPGA engineer for a new pioneering project. As a team, you will co-work with BIOS, SW and HW expertise and tightly engaged with customers. In this position, you will be responsible for understanding Intel provided IP blocks, delivering training to customers, troubleshooting issues and implementing new IP blocks.

Responsibilities for this position would involve but not be limited to:

Engage customer to understand customer’s need about IP  or reference design Work with team to define IP block and reference design architecture Work with team to develop IP block/reference design and get it pass validation Engage customer’s technical influencer to drive IP and reference design’s adoption Build collateral and guide customer to use our IP block and reference design Assist debugging with customer’s design and clarify issues when Intel IP blocks are used Consolidate feedback to contribute to product definition


Must have a Bachelors or Masters in Computer Science, Computer Engineering, Electrical Engineering or related fields Minimum of 6 years of FPGA/RTL design experience  at the master level Minimum of 8 years of FPGA/RTL design experience at the bachelor level Development experience with system, e.g.  wireless, storage, and computer Good English communication skills, both written and oral Disciplined design approach, and ability to work smoothly with a team.

Additional Qualification and Experience would be helpful

Knowledge of CPU architecture, general GPU architecture, and network accelerators, Prior experience working with heterogeneous (FPGA, CPU, GPGPU) hardware systems, Subject matter expertise in a particular class of algorithms, e.g. speech, cryptography, compression, image processing, packet processing, and etc. Knowledge in latest design methodology like CUDA, OpenCL and HSA.  



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