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Formal verification and Low Power Validation Lead


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Formal verification and Low Power Validation Lead Careers at Intel in Bangalore, KA
Job ID: JR0056086
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Formal verification and Low Power Validation Lead

Job Description
As a key member of CHG GMD fullchip integration team, you will be responsible for all aspects of Formal verification and Low power validation for our next generation Graphics full chip development. Responsibilities include drive Formal verification and Low Power validation methodologies, executions that includes hands on logic equivalence checking/static signoff experience. Responsible in creating necessary setup and guidance flow for conformal LEC/CLP flows, debugging the failures and identifying the structural failures. Optimal ECO development through conformal-ECO and develop TCL-based scripts to aide closure. Good understanding in low power designs. Experience in faster debugging for LEC failures in high datapath intensive designs. Hands On experience in coding UPF and exposure to SpyGlass based low power validation flows.


- Should possesses a Master's Degree in VLSI with minimum 6 to 8 Yrs experience--- Should have good understanding of Logic equivalence checking using LEC and debugging skills, low power design validation, Conformal ECO flows- experience of PERL/Python, TCL, Linux, Shell.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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