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DFT - Validation Engineer

Intel


Location:
Santa Clara, CA
Date:
09/25/2017
2017-09-252017-10-24
Job Code:
JR0035634
Categories:
  • Engineering
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Job Details

DFT Careers at Intel in Validation Engineer
   
Job ID: JR0035634
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations: US, California, San Diego;
Job Type:

DFT - Validation Engineer

Job Description

Design for test role in the baseband modem hardware solutions for Baseband SOC group. The position is for a DFT/Validation engineer inside the DFT methodology and flow development team within the BSD group.

In this position you will be responsible for developing and proving the DFT solutions that will eventually be implemented in BBIC products. You will be responsible to enable and ensure that all products meet DFT requirements inside the BBIC. Interface with other teams to review their implementation of the DFT architecture.

The position also involves close collaboration with pre-silicon and post-silicon team to ensure robust validation and hitting the required coverage goals. 

  • You will create functional test vectors working with the front end design/emulation teams to convert VCD patterns to test vectors.
  • You will be working with the test engineer in executing and bringing up functional, scan, mbist patterns on silicon.


The candidate much be able to have effective communication and interaction with design teams as well as central IP delivery teams. Candidate must be self-motivated and take up all required initiatives to gather the state of the art DFT solutions, identify applicability to 5G BBIC products and drive towards getting the solutions implemented on next generation products. Candidate must be able to effectively communicate with peers and managers. 

Minimum Qualifications:

BSEE and 10+ years in Design and DFT experience

MSEE and 7+ years with DFT experience

  • Expertise in DFT solutions around Scan based logic testing as well as memory testing
  • Expertise in DFT insertion in design with multiple power domains, asynchronous clock domains and voltage islands.
  • Experience in DFT EDA tools like Mentor Tessent.
  • Expertise in RTL design, Synopsys DC, Prime Time, CDC.
  • Experience to debug patterns on tester in ATE environment.
  • Understanding of SOC design flows

Preferred Qualifications: 

  • Verilog/System Verilog proficiency is required.
  • FPGA usage with ARM debugger is preferred.
  • C / C++ programming skills are highly desired.
  • Proficiency with scripting languages like Tcl, Perl, Python



Qualifications

Inside this Business Group

Intel is one of the largest suppliers of chips for the communications market. The Intel Communications group is focused on designing and building communications technologies such as Ethernet connectivity products, optical components, communications processing solutions and broadband products.



Other Locations
US, California, San Diego;


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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