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Design Verification Engineer

Intel


Location:
San Jose, CA
Date:
08/23/2017
2017-08-232017-09-21
Job Code:
JR0033068
Categories:
  • Engineering
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Job Details

Design Verification Engineer Careers at Intel in San Jose, CA
   
Job ID: JR0033068
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations:
Job Type:

Design Verification Engineer

Job Description

As part of Intel, we will continue to apply Moore’s Law to drive the future of field-programmable gate array (FPGA) technology.  The Programmable Solutions Group (PSG) has been delivering industry-leading custom logic solutions to customers since inventing the world's first reprogrammable logic device in 1984.  In order to take advantage of the many opportunities that we see in the future for FPGA’s, PSG is looking for great Design Verification Engineers to join our team.

Intel Programmable Solutions Group (PSG) is focusing on development of FPGAs and associated IP products for the Advanced Driver Assistance Systems (ADAS) market. As such these products need to comply with Functional Safety requirements. The IP Functional Safety Engineer will be responsible for executing the Functional Safety process to ensure that PSG IP meets the requirements.

Duties will include: 

- Executing safety analysis (Failure Mode Effect and Diagnostic Analysis, Fault Tree Analysis) on PSG IP products

- Identifying and characterizing mitigation measures for preventing or detecting faults potentially affecting integrated circuits

- Executing fault injection testing to verify the performance of such mitigation measures

- Preparing and maintaining of specific documents and data like functional specifications, safety analysis reports, and safety verification plans

Please be informed that Intel is proactively trying to find candidates for a position and that may, or may not, be available for all location(s) at this time. If you're interested in this position, should it become available, we encourage you to apply, and our hiring team will be glad to contact you when relevant.



Qualifications
- MSEE or related degree with 2+ years of experience in SoC/IP design, in functional verification of digital circuit and/or front to back digital design flow (or similar) OR BSEE or related degree with 4+ years of similar experience. - Experience in HDL such as Verilog, VHDL, UVM/OVM ADDITIONAL (PREFERRED) QUALIFICATIONS - MSEE or related degree with 2+ years of experience in SoC/IP design, preferably in functional verification of digital circuit and/or front to back digital design flow OR BSEE or related degree with 4+ years of similar experience. - Knowledge of functional safety basics, related standards such as IEC 61508 and ISO 26262, Failure Modes, Effects and Diagnostics Analysis (FMEDA) and Fault Tree Analysis (FTA) processes - Knowledge in PCIe Protocol - Knowledge of requirement management tools like IBM DOORS Next Generation - Knowledge in any scripting language (e.g. Python) is a plus


Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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