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Design Verification Engineer


San Jose, CA
Job Code:
  • Engineering
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Job Details

Design Verification Engineer Careers at Intel in San Jose, CA
Job ID: JR0032318
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations:
Job Type:

Design Verification Engineer

Job Description


The successful candidate's minimum qualifications will include the following:

•             BS in Electrical Engineering, Computer Engineering, or equivalent with a minimum of 5+ years of experience verifying complex ASICs

•             Strong background in PCIe or Ethernet protocols

•             Experience with HW/SW debug

•             Experience with 3rd party verification IPs

•             Hands-on experience with SystemVerilog UVM

•             Knowledge of modern Testbench and Regression flows

•             Good knowledge of scripting languages

•             Attention to details, and excellent verbal and written communication skills

Intel (PSG) is looking for an experienced Design Verification Engineer to verify PCIe or Ethernet Protocol IP. You will be part of the team that assures that our design is functionally correct and meets defined requirements. Your specific responsibilities will include but are not limited to the following: • Development and integration of verification environment components utilizing UVM/SystemVerilog • Testbench Development • Creating Verification/Test plans from Functional Specifications • Development, simulation and debug of UVM and C based test cases • Coverage analyses

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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