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Debug Design Validation Engineer

Intel


Location:
Jeralem, IL
Date:
10/20/2017
2017-10-202017-11-18
Job Code:
JR0038637
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Job Details

Debug Design Validation Engineer Careers at Intel in Jerusalem,
   
Job ID: JR0038637
Job Category: Intern/Student
Primary Location: Jerusalem, IL
Other Locations:
Job Type: Intern

Debug Design Validation Engineer

Job Description
A candidate for a temporary position who has not yet graduated and is working towards a relevant Bachelor's, Specialist's, Technical, Master's or PhD degree from a relevant academic institute. A Student employee can do specific work in the area of their future degree or work as a Generalist in a specific department. The Studentship is limited in time with the intent to hire into an College Graduate/Technical Graduate position as appropriate.


Qualifications

Minimum Qualifications:

BSEE or equivalent, studying toward second degree is an advantage.

Minimum 4 days of availability for work

Preferred Qualifications:

Direct experience with SerDes or high-speed IO IP post-silicon validation

Optimizing post-silicon lab automation and environments

Knowledge of Python, or similar scripting language, for post-silicon validation.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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