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Core Layout Design Engineer

Intel


Location:
Bangalore
Date:
09/18/2017
2017-09-182017-10-17
Job Code:
JR0036287
Categories:
  • Engineering
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Job Details

Core Layout Design Engineer Careers at Intel in Bangalore, KA
   
Job ID: JR0036287
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: Experienced Hire

Core Layout Design Engineer

Job Description

Candidate must possess a Master's Degree in VLSI or Electricals or equivalent with at least 2 years of experience in related field or a Bachelor's Degree in E&C or Electrical Engineering or equivalent with at least 4 or more years of experience or Diploma in E&C with at least 6 years of experience.

Preferred Experience: -Layout design of high speed Datapath or Register file or custom memory-Understanding of Layout design Convergence at Block/Section Level -Basic understanding of timing analysis is plus-Scripting knowledge is plus -Strong verbal and written communication skills


Qualifications

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

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