Sign In
 [New User? Sign Up]
Mobile Version

Chip-Package CoDesign Engineer for RF Wireless Products (f/m)

Intel


Location:
Munich, DE
Date:
10/18/2017
2017-10-182017-11-16
Job Code:
JR0038471
Categories:
  • Engineering
  •  
  • Save Ad
  • Email Friend
  • Print
  • Research Salary

Job Details

ChipCareers at Intel inPackage CoDesign Engineer for RF Wireless Products (f/m)
   
Job ID: JR0038471
Job Category: Engineering
Primary Location: Munich, DE
Other Locations:
Job Type:

Chip-Package CoDesign Engineer for RF Wireless Products (f/m)

Job Description

Microelectronic Packaging Engineers provide project management, package design/development and sustaining support for integrated circuit or semiconductor assemblies, various other electronic components and/or completed units. Responsible for the thermal/mechanical/electrical design, analysis, and development of electronic packages. Defines overall package performance and specification and realizes technology certification through layout design and test vehicle design. Conducts tests and research on basic materials and properties. Establishes material specifications for contract assemblers and raw material vendors and interfaces with Quality Assurance and Purchasing regarding material quality and vendor performance. Provides consultation concerning packaging problems and improvements in the packaging process. Responds to customer/client requests or events as they occur. Develops solutions to problems utilizing formal education and judgment.

  • Focus on iCDG key technologies for mobile, access to the cloud and always-connected world IoT.
  • Responsible for Chip-Package-Board-CoDesign project setup, data management and design flow maintenance.
  • Integrate pin list changes with pads in golden Chip-Package-CoDesign database.
  • Responsible for pad placement & optimization with risk assessment.
  • Bump-out Matrix definition & modifications according to the technology node spec.
  • Interface between Chip/Package designers & Probe Card/Test boards (TIU/SIU) designers.
  • Responsible for Substrate Connectivity Check.
  • Responsible for the Daisy-Chain setup, concept and flow.

Expertise and knowledge

  • College Graduate role that requires technical background or relevant work experience.
  • Experience with Mentor / Cadence package layout tools.
  • Knowledge on Chip-Floor-Planning and PCB test board design.
  • Linux operating systems
  • Data Management Systems
  • English spoken and written

Please be informed that Intel is proactively trying to find candidates for this position which is frequently available at Intel Deutschland. Please note that the position may not be available at this time. If you would be interested in this position should it become available, we would encourage you to apply, and our hiring team will be glad to contact you when/if relevant.



Qualifications

Inside this Business Group

Communication & Devices Group: The wireless revolution at Intel! We are one team - passionate engineers and technologists from diverse industry backgrounds working together to realize a world of connected computing. We are bringing the best ideas from the brightest minds to deliver future mobile experiences into the market. We are on the journey towards making Intel a wireless leader with exciting products for the Internet of Things, 5G and an opportunity to change the world with your work.

   

As an electronics industry innovator and a leader in corporate responsibility, we look for ways to apply our technology to address global challenges while serving as a role model for how companies should operate.

Powered By

Featured Employers

Featured Jobs