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Atom CPU Soft-IP Enablement Engineer

Intel


Location:
Atin, TX
Date:
04/06/2018
2018-04-062018-05-05
Job Code:
JR0046431
Categories:
  • Engineering
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Job Details

Atom CPU SoftCareers at Intel inIP Enablement Engineer
   
Job ID: JR0046431
Job Category: Engineering
Primary Location: Austin, TX US
Other Locations:
Job Type: Experienced Hire

Atom CPU Soft-IP Enablement Engineer

Job Description

In this position, you are entrusted to working directly with internal and external SoC customers, enabling them to harden Atom CPU Soft-IP (SIP) in a foundry of their choice. In addition, you will work on state-of-the-art tools, flows and methodologies, to provide a reference for customers to harden the Atom Core. This position requires candidates who are strong in RTL2GDS design, flow, and methodology implementation. Requires the ability to work independently and multitask effectively. Must exhibit persuasive skills both within the Atom team and with customers, and be customer-focused in a dynamic and changing environment. Some amount of domestic and international travel may be required.

Responsibilities:

  • Physical design and development of Atom CPU
  • Static timing analysis, variation modeling, and verification of high-speed process design
  • Running Synopsys DC and ICC flow for synthesis, and APR for a trial convergence ahead of customer use
  • Layout verification and debug of customer design issues
  • Respond to customers’/clients’ requests or events as they occur
  • Work with domain experts in the Atom organization (in RTL, verification, DFx, compilers, etc.)


Qualifications

  • Master’s Degree in Electrical Engineering or Computer Engineering
  • 8 – 10+ years’ experience in latest RTL2GDS design and methodology development.
  • Strong background and expertise in the following areas are a must:
    • Latest (16 nm/14 nm and beyond) design and layout challenges
    • Expert knowledge and experience with design convergence and flow development
    • Experience in Synopsys Design Compiler, IC Compiler, IC Compiler II, StarRC, Primetime Suite, and Cadence Conformal
    • Prior CPU design or hardening experience
    • Experience in hardening 3rd party IP in custom foundry is a plus
    • Scripting skills using Perl/Tcl
    • Deep understanding and knowledge of Static Timing Analysis
    • Latch based design closure
  • Must be able to work independently on various customer design issues (mostly back-end)

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.


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