ASIC DFT Lead Hardware Engineer

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Hardware
  • Job Type
  • Technology Interest
    Service Provider
  • Job Id

ASIC Design for Test - Hardware Engineer

Location: San Jose, CA

"Who You'll Work With" 

Our creative and talented team as Design for Test Hardware Engineer in San Jose, CA. You will work with ASIC Front-end RTL teams, backend physical design teams to understand chip architecture and drive design for test requirements early in the design cycle. As a member of this team you will be involved in creating cutting edge next generation networking chips. You will be the lead to drive the DFT and quality process through the entire Implementation flow. 

"What You'll Do"

  • Responsible for implementing the ASIC Hardware Design-for-Test (DFT) features that supports the in-system test, debug and diagnostics needs of the design.
  • Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in the RTL
  • Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow.  
  • Your team will be responsible for Innovative Hardware DFT for new silicon device models, including silicon photonic chipsets, bare die, stacked die and 2.5D and 3D and driving re-usable test and debug strategies.  
  • The job requires the candidate to have good scripting skills and the ability to design and debug with minimal oversight.

"Who You Are" 

You are an ASIC Design for Test Hardware Engineer with 8+ years of related work experience with a broad mix of technologies including: 

  • Excellent knowledge of latest state-of-the-art trends in DFT and test.
  • Hands-on experience with Jtag protocols, Scan and BIST architectures, including Logic BIST, memory BIST, IO BIST
  • Verification skills include, System Verilog, UVM, Logic Equivalency checking and validating the Test-timing of the design.
  • Experience working with Gate level simulation, and debug with VCS and other simulators.
  • Post-silicon validation  and debug experience; Ability to work with ATE patterns, P1687
  • Strong verbal communication skills and ability to thrive in a dynamic environment
  • Scripting skills: Python/Perl.
  •  Bachelor's or a Master’s Degree in Electrical or Computer Engineering required

"Why Cisco"
We connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren’t afraid to change the way the world works, lives, plays and learns. 

We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers. 

We Are Cisco.


We connect everything - people, process, data and things. We innovate everywhere to create fresh ideas and possibilities. We make a meaningful difference that will benefit everyone - our people, our customers and the world around us.

Our technology changes the way the world works, lives, plays and learns. But our edge doesn't come from technology. It comes from our people. We're looking for the kind of people who take smart risks, thrive in diverse environments, inspire their colleagues, and are committed to having an impact on the world. Whether you create technology solutions that redefine business or build connections that strengthen the community, you can make it happen at Cisco!

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